The present disclosure relates to a hardware apparatus for a system, to a system and to a memory access method.
A system in the form of a computer usually has a central control unit (CPU=Central Processing Unit) which can access a main memory. The central control unit is connected to a system bus, such as a PCI bus (PCI=Peripheral Component Interconnect), a PCI-X bus, a PCIe bus (PCI express bus), etc., and is connected via the latter to other hardware apparatuses of the computer. Such hardware apparatuses are an integrated circuit, for example, which may be a field programmable gate array (FPGA), in particular. If the hardware apparatuses have master capability, which means that they themselves can control other appliances or apparatuses, then they can use direct memory access (DMA) to send and receive data, particularly in the form of data packets, independently without the central control unit being used in the process. This relieves the load on the central control unit for data flow control in the computer.
As standard, the data flow control is implemented by reading status registers in the hardware apparatus, such as the field programmable gate array (FPGA). This requires a read cycle on the system bus. Such read cycles on the system bus last an extremely long time, however. This is accompanied by the central control unit being stopped for the time of the read cycles. This takes up valuable computation time which would otherwise be available to the central control unit.
The loading of the central control unit with respect of time in the prior art is calculated from the fact that a single read cycle on the bus lasts between 0.6 μs and 1 μs, depending on system components. This time may also be much longer, since, in the case of a PCI bus, in the worst case, a single access operation can even also be extended by up to 7.6 μs if the bus is occupied by ongoing direct memory access (DMA) with a maximum waiting time (waiting time counter (latency counter)→255*30 μs).
DE 38 30 723 A1 describes a device for direct memory access (DMA) to a main memory of a computer which is connected to a system bus.
Furthermore, it is known practice to perform data flow control using interrupt requests. However, such a solution is not possible or meaningful in every system or computer. In addition, such a solution takes up even more computation power. A further problem is that there is usually also not enough free interrupt line available.
It is therefore an object of the present disclosure to provide a hardware apparatus for a system, a system and a memory access method which can be used to solve the aforementioned problems.
In particular, the aim is to provide a hardware apparatus for a system, a system and a memory access method in which the central control unit (CPU) is relieved of load for the data flow control. This object is achieved by a hardware apparatus as described herein.